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ALOXTM¶ó´Â Çõ½ÅÀûÀÌ°í µ¶Ã¢ÀûÀÎ substrate¸¦ °³¹ßÇØ ¿Ô½À´Ï´Ù.
ALOXTM´Â microelectronics. Packaging °°Àº ÀÀ¿ëºÐ¾ß¸¦ °³¹ßÇϱâ À§ÇÑ µ¶Æ¯ÇÑ multilayer substrateÀÔ´Ï´Ù.
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ALOXTM¿¡´Â Via¿Í ±× via¸¦ ÅëÇÑ platingÀÌ ÇÊ¿ä ¾ø½À´Ï´Ù. Via´Â ¾Ë·ç¹Ì´½°ú °íǰÁúÀÇ ¼¼¶ó¹Í Ư¼ºÀÇ À¯Àü¹°Áú·Î ä¿öÁ® ÀÖ½À´Ï´Ù. ´Ü¼øÇÑ Á¦Á¶°øÁ¤°ú ³·Àº Á¦Á¶ºñ¿ë °øÁ¤¼ö°¡ Àû½À´Ï´Ù.
ALOXTM technology´Â ³ÐÀº ¿µ¿ªÀÇ technical platformÀ» °¡´ÉÇÏ°Ô Çϰí RF, SIP, 3-D memory stack, MEMS, High power module°ú componentµî°ú °°Àº ´Ù¾çÇÑ Á¾·ùÀÇ packagingÀû¿ëÀ» °¡´ÉÇÏ°Ô ÇÕ´Ï´Ù.
ÇöÀçÀÇ laminate/build-up substrate ³ª ceramic substrate¿¡ ºñ±³ÇÏ¿© ALOXTM substrateÀÇ ÀåÁ¡Àº ¿ì¼öÇÑ technical performance¿Í cost¿¡ ÀÖ½À´Ï´Ù.
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º¹ÇÕÀûÀÎ ¾Ë·ç¹Ì´½ heat-sinkÀÇ ³»ÀåÀ¸·Î ÀÎÇÑ ¿ì¼öÇÑ thermal property
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Very high routing density ­metal line/space : 1/1mil
RF Àû¿ëÀ» À§ÇÑ Æ¯º°»çÇ× - strip lines,?wave guide structures, controlled impedance lines.
integrated passives option - resistors in the multilayer
 
°¡°Ý°æÀï·Â
PCB type substrate¿¡ ºñÇÏ¿© »ó´çÈ÷ ³·Àº ¼öÁØÀÇ Á¦Á¶ºñ¿ë ? drilling, hole platingÀÌ ÇÊ¿ä ¾øÀ½.
±âº»ÀûÀ¸·Î ALOX´Â ceramic ±â¹ÝÀÇ substrate¸¦ Á¦°øÇϸç PCBÀÇ °øÁ¤ ¼ö¿¡ ºñÇÏ¿© ÃÖ¼Ò°øÁ¤À¸·Î Á¦À۵˴ϴÙ.
Design Guide
Aloxtm Substrate, Technical Specification
     
Total Thickness §­ 75-300 Typical 100-200. Very low profile! Less than 50% of convention profile!
Internal aluminum layer Line/space §­ 100/100 Used for ground and power layers,
Very fine resolution for the application!
Internal aluminum layer Thickness §­ 30-140 Option for very heavy ground and power layers.
Top % Bottom layers line/space
Top Copper layer thickness
§­ 25/25
6-20-35
Current Minimum , Cutting edge resolution!
Typical s, Heavier copper traces can be fabricated
Via width/pitch(min) §­ 140/250 For substrate thick of 125§­. Current cutting edge resolution for Core
applications
Via Pad(=Land size) (min)(For
Substrate. Thickness of 125§­.)
§­ 40 Land size equal to pad is impossible to achieve in conventional
technology. Typically for conventional boards land size is three times
the pad size.
Dramatic advantage for ALOX in terms of routing density!
Finish s(Typical) Nickel/Gold 5/0.2 §­&
Solder mask
Typical
Mechanical and Thermal s
Young Modulus(E) Mpa 130 Very high and clear advantage over plastics
Poison Ratio(V) - 0.29  
Thermal Coefficient of Expansion
(TCE)
ppm/deg 7.8 This is adjustable. is ranging from 8-12. Great advantage
over plastics in matching properties to the silicon die.
Flexural Strength Mpa 60,0000
Thermal Conductivity of the Dielectric Watt/mxdeg 12-20 Property of the Dielectric. Significant advantage.
Integral Heat Sink option!
Operating temperatures Degs. <300¡É Extendable to <350¡É;
Reliability
1000 thermal cycles test, 1000 vias
chain, 0.5§® pitch
% chain
resistance
change .
<3%
Pass
-55¡É toi +125¡É
JESDC 22-A104-B / PASS!
Electrical Data
Dielectric Constant 50 Mhz-20 GHz   6.6 Outsource measure
Dissipation Factor 50 Mhz-20 GHz   <1.2% Outsource measure
Withstand Voltage @40 §­ Volts 1000(25Volts/§­) MCL measurement
Via Series Resistance Via chain   <10§Û MCL measurement
Via inductance Dtop=50 §­
H=200§­
Dcenter=250§­
pH 8.4¡¾10% Calculation
Blind Via inductance   pH 4.2¡¾10% Calculation
Via Capacitance        
Resistivity of Cu traces @20§­ and 10§­
respectively
§Ù/square. 0.0017-0.0025 MCL measurements
Type of Impedance Line   NA Microstrip Strip lines,
differncial.
 
Options   NA Split in ground/voltage layer,
large vias
 
Characteristic
impedance for
transmission line
    25-100§Ù Outsource measure + estimate
Impedance line
tolerance
    ¡¾10% Estimated
Delay   ps/inch 160-180 Outsource measure
Optional-Integral Coils     Integral Coils  
Leakage current(Rvia-g) @500Volts §Ù 10exp13 TV2(Outsource)
Leakage current(Rz) @150Volts §Ù §¯ 3*10exp12 TV2(Outsource)
Surface resistance(Rs) @150Volts §Ù/sq 3*10exp13 TV2(Outsource)